1. Field of the Invention
The present invention relates to an integrated circuit having a dual-port memory.
2. Description of the Prior Art
A dual-port memory allows access to a memory cell to perform a read or a write operation from two functionally independent ports. One form of dual-port memory used in computer graphics applications includes "slow" and "fast" ports. The "slow" port allows both reading information from, and writing information to, the memory cell, and hence is also referred to as a "read/write" port. The "fast" port allows only reading information from the memory cell, and hence is also referred to as a "read-only" port. These speed designations are relative, and in one present-day integrated circuit technology, the cycle times for these operations are 100 nanoseconds and 7 nanoseconds, respectively. Furthermore, increases in speed will be achieved in future generations of technology. This type of dual-port memory is useful in graphics-display type applications that require a read/write port for interaction with a microprocessor or other device that supplies information to be displayed. The read-only port supplies data to a digital-to-analog converter for display on a video screen.
A problem in implementing a dual port memory having a fast read-only port and a slow read/write port concerns disturbances that could degrade a fast read operation. One type of disturbance between the ports, and one type of solution, is shown in U.S. Pat. No. 4,905,189. However, the solution provided therein requires extra transistors in the cell to isolate disturbances, which are said to be between a write operation and a simultaneous read operation. Also, both ports communicate to the cell through n-channel access devices, which causes added complexity to the cell layout when the two row-line conductors are located adjacent to each other. The cell layout area is typically increased as a result. It would therefore be desirable to obtain a dual-port memory that minimizes disturbances between the ports while allowing for a compact cell layout and a reduced number of devices.